1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device having a CMOS dual-gate electrode structure; that is, a polymetal gate electrode structure which prevents interface resistance from arising between polysilicon and a metal film while suppressing interdiffusion and depletion of polysilicon of the gate electrode, as well as to a method of manufacturing the semiconductor device.
2. Background Art
In general, a CMOS structure has widely been used in the field of semiconductor devices, because of its low power dissipation characteristic.
FIG. 13 is a top view showing a related-art semiconductor device. The drawing shows an inverter, which is the basic circuit of CMOS structure, wherein an n-channel transistor and a p-channel transistor are fabricated on a single chip. FIG. 14 is a cross-sectional view of the inverter taken along line A-Axe2x80x2, and FIG. 16 is a cross-sectional view of the inverter taken along line B-Bxe2x80x2.
In these drawings, reference numeral 101 designates a silicon substrate; 105 designates an isolation region; 108 designates an active region; 110 designates a P-well; 115 designates an N-well; 130 designates a gate electrode; 130a designates a polysilicon film; 130b designates a barrier layer; 130d designates a metal film; 140 designates an insulating film formed on top and side of a gate electrode; 150 designates a P+-source/drain electrode; 160 designates an interlayer insulating film; 170 and 175 designate contact holes; and 180 and 180a through 180c designate interconnection.
In order to achieve higher packaging density, the gate electrode 130 is shared between the n-channel transistor and the p-channel transistor. If the gate electrode 130 shared between the n-channel transistor and the p-channel transistor is separated, separated gate electrodes must be interconnected together on an interconnection layer by way of contact holes, thus involving provision of additional space for the contact holes.
Shortening of a channel of a gate electrode has recently been pursued for achieving a higher packaging density. The dominating p-channel transistors are of related-art embedded channel type and cannot sustain a short-channel effect. As in the case of an n-channel transistor, the p-channel transistor must be changed to a surface channel type, and the conductivity type of gate electrodes must be changed as well.
As shown in FIG. 14, before a non-doped polysilicon gate electrode deposited on a gate oxide film is subjected to etching, an n-channel region is doped with n+ ions. Further, a p-channel region is doped with p+ ions. As a result, an n+-type region and a p+-type region coexist in a single gate electrode. A reduction in the length of a channel of the gate electrode; that is, a reduction in the thickness of the gate electrode, involves a rise in the resistance of the polysilicon gate electrode. In order to reduce the resistance of the polysilicon gate electrode, a metal film 130d must be deposited on the polysilicon film 130a. 
A structure in which the metal film 130d is laid over the polysilicon film 130a encounters the following problems, and hence a layer called a barrier layer 130b is interposed between the metal film 130d and the polysilicon film 130a. One problem is that a reaction between the metal film 130d and the polysilicon film 130a; that is, a silicide reaction, arises, thereby inducing occurrence of holes in the polysilicon film 130a. Another problem is that impurities doped in the polysilicon film 130a diffuse into metal or into a compound of metal with polysilicon, thereby reducing a net density of impurities doped in one of adjacent transistors of opposite conductivity types.
Forming the barrier layer 130b solves these problems. However, the barrier layer 130b is usually a metal nitride film and deficient in conductivity. A contact hole to be connected to a gate electrode extends to the metal film 130d from above. In fact, a channel is not established unless an electric field is applied to the lower polysilicon film 130a. In this way, if the barrier layer 130b is sandwiched between the polysilicon film 130a and the metal film 130d, high interface resistance arises between the metal film 130d and the polysilicon film 130a. As a result, a delay arises in transfer of a voltage, as shown in FIG. 15. Such a delay is one cause of a delay time in a logic gate typified by an inverter or a NAND.
As mentioned above, a polymetal gate electrode of a related-art semiconductor device is constructed of a three-layer structure consisting of a metal film, a nitrided metal film, and a polysilicon film, where a barrier layer induces a rise in interface resistance between the nitrided metal film and the polysilicon film, thereby reducing the speed of the overall LSI.
The purpose of the present invention is to provide a semiconductor device having a new gate electrode structure and a method of manufacturing the semiconductor device. The gate electrode structure according to the present invention reduces interface resistance between a barrier layer and a polysilicon film and to prevent occurrence of a delay in transfer of a voltage in the polymetal gate electrode.
According to one aspect of the present invention, a semiconductor device comprises a gate electrode structure including at least a metal film and a polysilicon film, wherein the polysilicon film is doped with impurities several times. As a result an upper portion of the polysilicon film becomes higher in doping level than a lower portion of the same.
In other aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of forming a polysilicon film on a semiconductor substrate; forming a barrier layer from a plurality of layers on the polysilicon film; and forming a metal film on the barrier layer.
In other aspect of the present invention, a method of forming a semiconductor device comprises the steps of forming a polysilicon film on a semiconductor substrate; doping the polysilicon film with impurities a plurality of times; and forming a metal film on the impurity-doped polysilicon film.
Other and further objects, features and advantages of the invention will appear more fully from the following description.